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w5500.h
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1 
13 #ifndef _W5500_H_
14 #define _W5500_H_
15 
16 //#include "Types.h"
17 
18 #define IINCHIP_ISR_DISABLE() __disable_fault_irq()
19 #define IINCHIP_ISR_ENABLE() __enable_fault_irq()
20 
21 //----------------------------- W5500 Common Registers : WIZC_Reg -----------------------------
22 #define WIZC_MR (0x0000)
23 #define WIZC_GAR0 (0x0001)
24 #define WIZC_SUBR0 (0x0005)
25 #define WIZC_SHAR0 (0x0009)
26 #define WIZC_SIPR0 (0x000F)
27 #define WIZC_INTLEVEL0 (0x0013)
28 #define WIZC_INTLEVEL1 (0x0014)
29 #define WIZC_IR (0x0015)
30 #define WIZC_IMR (0x0016)
31 #define WIZC_SIR (0x0017)
32 #define WIZC_SIMR (0x0018)
33 #define WIZC_RTR0 (0x0019)
34 #define WIZC_RCR (0x001B)
35 #define WIZC_PTIMER (0x001C)
36 #define WIZC_PMAGIC (0x001D)
37 #define WIZC_PHA0 (0x001E)
38 #define WIZC_PSID0 (0x0024)
39 #define WIZC_PMR0 (0x0026)
40 #define WIZC_UIPR0 (0x0028)
41 #define WIZC_UPORT0 (0x002C)
42 #define WIZC_PSTATUS (0x002E)
43 // Reserved (0x002F)
44 // Reserved (0x0030)
45 // Reserved (0x0031)
46 // Reserved (0x0032)
47 // Reserved (0x0033)
48 // Reserved (0x0034)
49 // Reserved (0x0035)
50 // Reserved (0x0036)
51 // Reserved (0x0037)
52 // Reserved (0x0038)
53 #define WIZC_VERSIONR (0x0039)
56 //----------------------------- W5500 Socket Registers : WIZS_Reg -----------------------------
57 #define CH_SIZE (0x0100)
59 #define WIZS_MR (0x0000)
60 #define WIZS_CR (0x0001)
61 #define WIZS_IR (0x0002)
62 #define WIZS_SR (0x0003)
63 #define WIZS_PORT0 (0x0004)
64 #define WIZS_DHAR0 (0x0006)
65 #define WIZS_DIPR0 (0x000C)
66 #define WIZS_DPORT0 (0x0010)
67 #define WIZS_MSSR0 (0x0012)
68 // Reserved (0x0014)
69 #define WIZS_TOS (0x0015)
70 #define WIZS_TTL (0x0016)
71 // Reserved (0x0017)
72 // Reserved (0x0018)
73 // Reserved (0x0019)
74 // Reserved (0x001A)
75 // Reserved (0x001B)
76 // Reserved (0x001C)
77 // Reserved (0x001D)
78 #define WIZS_RXMEM_SIZE (0x001E)
79 #define WIZS_TXMEM_SIZE (0x001F)
80 #define WIZS_TX_FSR0 (0x0020)
81 #define WIZS_TX_RD0 (0x0022)
82 #define WIZS_TX_WR0 (0x0024)
83 #define WIZS_RX_RSR0 (0x0026)
84 #define WIZS_RX_RD0 (0x0028)
85 #define WIZS_RX_WR0 (0x002A)
86 #define WIZS_IMR (0x002C)
87 #define WIZS_FRAG (0x002D)
88 #define WIZS_KPALVTR (0x002F)
89 #define WIZS_TSR (0x0030)
92 //----------------------------- W5500 Register values -----------------------------
93 /*
94  @brief Sn_TSR Values
95  */
96 #define TS_SEND_ACK (0x04)
97 #define TS_WAIT_ACK (0x02)
98 #define TS_DISABLE (0x01)
99 
100 #define TESTREG (0x0050)
101 #define TESTREG_VAL10 (0x0051)
102 #define TESTREG_VAL11 (0x0052)
103 #define TESTREG_VAL12 (0x0053)
104 #define TESTREG_VAL13 (0x0054)
105 #define TESTREG_VAL20 (0x0055)
106 #define TESTREG_VAL21 (0x0056)
107 #define TESTREG_VAL22 (0x0057)
108 #define TESTREG_VAL23 (0x0058)
109 
110 /* MODE register values */
111 #define MR_RST 0x80 //< reset */
112 #define MR_WOL 0x20 //< Wake on Lan */
113 #define MR_PB 0x10 //< ping block */
114 #define MR_PPPOE 0x08 //< enable pppoe */
115 #define MR_MACRAW_NOSIZECHK 0x04 //< enbale MACRAW NO SIZE CHECHK */
116 #define MR_UDP_FORCE_ARP 0x02 //< enbale UDP_FORCE_ARP CHECHK */
117 
118 /* IR register values */
119 #define IR_CONFLICT 0x80 //< check ip confict */
120 #define IR_UNREACH 0x40 //< get the destination unreachable message in UDP sending */
121 #define IR_PPPoE 0x20 //< get the PPPoE close message */
122 #define IR_MAGIC 0x10 //< get the magic packet interrupt */
123 #define IR_SOCK(ch) (0x01 << ch) //< check socket interrupt */
124 
125 /* Sn_MR values */
126 #define Sn_MR_CLOSE 0x00 //< unused socket */
127 #define Sn_MR_TCP 0x01 //< TCP */
128 #define Sn_MR_UDP 0x02 //< UDP */
129 #define Sn_MR_IPRAW 0x03 //< IP LAYER RAW SOCK */
130 #define Sn_MR_MACRAW 0x04 //< MAC LAYER RAW SOCK */
131 #define Sn_MR_PPPOE 0x05 //< PPPoE */
132 #define Sn_MR_UNIBLOCK 0x10 //< Unicast Block in UDP Multicating*/
133 #define Sn_MR_ND 0x20 //< No Delayed Ack(TCP) flag */
134 #define Sn_MR_BROADBLOCK 0x40 //< Broadcast blcok in UDP Multicating */
135 #define Sn_MR_MULTI 0x80 //< support UDP Multicating */
136 
137 /* Sn_MR values on MACRAW MODE */
138 #define Sn_MR_MAWRAW_BCASTBLOCK 0xC0 //< support Broadcasting On MACRAW MODE */
139 #define Sn_MR_MAWRAW_MCASTBLOCK 0xA0 //< support IPv4 Multicasting On MACRAW MODE */
140 #define Sn_MR_MAWRAW_IPV6BLOCK 0x90 //< support IPv6 Multicasting On MACRAW MODE */
141 #define Sn_MR_MAWRAW_BCASTMCAST 0xE0 //< support Broadcasting On MACRAW MODE */
142 #define Sn_MR_MAWRAW_BCASTIPV6 0xD0 //< support Broadcasting On MACRAW MODE */
143 #define Sn_MR_MAWRAW_MCASTIPV6 0xB0 //< support Broadcasting On MACRAW MODE */
144 //#define Sn_MR_MAWRAW_MFENALE 0x10 //< support MAC Fileter Enable On MACRAW MODE */
145 
146 /* Sn_CR values */
147 #define Sn_CR_OPEN 0x01 //< initialize or open socket */
148 #define Sn_CR_LISTEN 0x02 //< wait connection request in tcp mode(Server mode) */
149 #define Sn_CR_CONNECT 0x04 //< send connection request in tcp mode(Client mode) */
150 #define Sn_CR_DISCON 0x08 //< send closing reqeuset in tcp mode */
151 #define Sn_CR_CLOSE 0x10 //< close socket */
152 #define Sn_CR_SEND 0x20 //< update txbuf pointer, send data */
153 #define Sn_CR_SEND_MAC 0x21 //< send data with MAC address, so without ARP process */
154 #define Sn_CR_SEND_KEEP 0x22 //< send keep alive message */
155 #define Sn_CR_RECV 0x40 //< update rxbuf pointer, recv data */
156 
157 #ifdef __DEF_IINCHIP_PPP__
158  #define Sn_CR_PCON 0x23
159  #define Sn_CR_PDISCON 0x24
160  #define Sn_CR_PCR 0x25
161  #define Sn_CR_PCN 0x26
162  #define Sn_CR_PCJ 0x27
163 #endif
164 
165 /* Sn_IR values */
166 #ifdef __DEF_IINCHIP_PPP__
167  #define Sn_IR_PRECV 0x80
168  #define Sn_IR_PFAIL 0x40
169  #define Sn_IR_PNEXT 0x20
170 #endif
171 #define Sn_IR_SEND_OK 0x10 //< complete sending */
172 #define Sn_IR_TIMEOUT 0x08 //< assert timeout */
173 #define Sn_IR_RECV 0x04 //< receiving data */
174 #define Sn_IR_DISCON 0x02 //< closed socket */
175 #define Sn_IR_CON 0x01 //< established connection */
176 
177 /* Sn_SR values */
178 #define SOCK_CLOSED 0x00 //< closed */
179 #define SOCK_INIT 0x13 //< init state */
180 #define SOCK_LISTEN 0x14 //< listen state */
181 #define SOCK_SYNSENT 0x15 //< connection state */
182 #define SOCK_SYNRECV 0x16 //< connection state */
183 #define SOCK_ESTABLISHED 0x17 //< success to connect */
184 #define SOCK_FIN_WAIT 0x18 //< closing state */
185 #define SOCK_CLOSING 0x1A //< closing state */
186 #define SOCK_TIME_WAIT 0x1B //< closing state */
187 #define SOCK_CLOSE_WAIT 0x1C //< closing state */
188 #define SOCK_LAST_ACK 0x1D //< closing state */
189 #define SOCK_UDP 0x22 //< udp socket */
190 #define SOCK_IPRAW 0x32 //< ip raw mode socket */
191 #define SOCK_MACRAW 0x42 //< mac raw mode socket */
192 #define SOCK_PPPOE 0x5F //< pppoe socket */
193 
194 /* IP PROTOCOL */
195 #define IPPROTO_IP 0 //< Dummy for IP */
196 #define IPPROTO_ICMP 1 //< Control message protocol */
197 #define IPPROTO_IGMP 2 //< Internet group management protocol */
198 #define IPPROTO_GGP 3 //< Gateway^2 (deprecated) */
199 #define IPPROTO_TCP 6 //< TCP */
200 #define IPPROTO_PUP 12 //< PUP */
201 #define IPPROTO_UDP 17 //< UDP */
202 #define IPPROTO_IDP 22 //< XNS idp */
203 #define IPPROTO_ND 77 //< UNOFFICIAL net disk protocol */
204 #define IPPROTO_RAW 255 //< Raw IP packet */
205 
206 /* Control Bits */
207 #define CB_SOCK_NUM 0xE0 //< 3bits : Socket[0-2] */
208 #define CB_MEM_SEL 0x10 //< 1bit : Memory Selection */
209 #define CM_MEM_DM 0xE0
210 #define CB_RXBUF_SOCKREG_SEL 0x08 //< 1bit : Socket RX Buffers or uint8 Registers Selection */
211 
212 #define CB_WRITE_EN 0x04 //< 1bit : Write Enable */
213 #define CB_SEQ_EN 0x02 //< 1bit : SEQ Enable */
214 
215 // < SPI Control Byte Structure for W5500 >
216 //
217 // | Control | : Byte
218 // =================================
219 // | Block Selector |Instruction| : Bits
220 // ---------------------------------
221 // | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
222 // ---------------------------------
223 // |Socket Num | Control Tail | : Meaning of Bits
224 // ---------------------------------
225 // * By way of exception, Control[7:3] bits '00000' choose the Common registers.
226 
227 #define CB_TAIL_COMMONREG_RD_SEQ 0x00
228 #define CB_TAIL_COMREG_RD 0x01
229 #define CB_TAIL_COMMONREG_WR_SEQ 0x04
230 #define CB_TAIL_COMREG_WR 0x05
231 
232 #define CB_TAIL_SOCKETREG_RD_SEQ 0x08
233 #define CB_TAIL_SOCKETREG_RD 0x09
234 #define CB_TAIL_SOCKETREG_WR_SEQ 0x0C
235 #define CB_TAIL_SOCKETREG_WR 0x0D
236 
237 #define CB_TAIL_TXBUF_RD_SEQ 0x10
238 #define CB_TAIL_TXBUF_RD 0x11
239 #define CB_TAIL_TXBUF_WR_SEQ 0x14
240 #define CB_TAIL_TXBUF_WR 0x15
241 
242 #define CB_TAIL_RXBUF_RD_SEQ 0x18
243 #define CB_TAIL_RXBUF_RD 0x19
244 #define CB_TAIL_RXBUF_WR_SEQ 0x1C
245 #define CB_TAIL_RXBUF_WR 0x1D
246 
247 
248 //----------------------------- Windowfull Control Values -----------------------------
249 #define WINDOWFULL_FLAG_ON 1
250 #define WINDOWFULL_FLAG_OFF 0
251 #define WINDOWFULL_MAX_RETRY_NUM 3
252 #define WINDOWFULL_WAIT_TIME 1000
253 
254 /*********************************************************
255 * iinchip access functions
256 *********************************************************/
257 //--Common register RD/WR
258 void IINCHIP_WRITE_COMMON( uint16 addr, uint8 data);
259 uint8 IINCHIP_READ_COMMON(uint16 addr);
260 void IINCHIP_READ_COMMON_SEQ(uint16 addr, uint8 len, uint8 * data);
261 void IINCHIP_WRITE_COMMON_SEQ(uint16 addr, uint8 len, uint8 * data);
262 
263 //--Socket register RD/WR
264 void IINCHIP_WRITE_SOCKETREG(uint8 sock_num, uint16 addr, uint8 data);
265 uint8 IINCHIP_READ_SOCKETREG(uint8 sock_num, uint16 addr);
266 void IINCHIP_READ_SOCKETREG_SEQ(uint8 sock_num, uint16 addr, uint8 len, uint8 * data);
267 void IINCHIP_WRITE_SOCKETREG_SEQ(uint8 sock_num, uint16 addr, uint8 len, uint8 * data);
268 
269 //--Socket TX&RX RD/WR
270 void IINCHIP_WRITE_TXBUF(uint8 sock_num, uint16 addr, uint8 data);
271 uint8 IINCHIP_READ_TXBUF(uint8 sock_num, uint16 addr);
272 void IINCHIP_WRITE_RXBUF(uint8 sock_num, uint16 addr, uint8 data);
273 uint8 IINCHIP_READ_RXBUF(uint8 sock_num, uint16 addr);
274 
275 void IINCHIP_WRITE_TXBUF_SEQ(uint8 sock_num, uint16 addr, uint16 len, uint8 * data);
276 void IINCHIP_READ_TXBUF_SEQ(uint8 sock_num, uint16 addr, uint16 len, uint8 * data);
277 void IINCHIP_WRITE_RXBUF_SEQ(uint8 sock_num, uint16 addr, uint16 len, uint8 * data);
278 void IINCHIP_READ_RXBUF_SEQ(uint8 sock_num, uint16 addr, uint16 len, uint8 * data);
279 
280 //-- Direct Access Mode
281 void IINCHIP_WRITE_DM(uint16 addr, uint8 data);
282 uint8 IINCHIP_READ_DM(uint16 addr);
283 
284 void IINCHIP_RXBUF_WRRD(uint16 addr, uint8 data);
285 
286 uint8 getISR(uint8 s);
287 void putISR(uint8 s, uint8 val);
288 uint16 getIINCHIP_RxMAX(uint8 s);
289 uint16 getIINCHIP_TxMAX(uint8 s);
290 
291 void setMR(uint8 val);
292 void setRTR(uint16 timeout); // set retry duration for data transmission, connection, closing ...
293 void setRCR(uint8 retry); // set retry count (above the value, assert timeout interrupt)
294 void setIMR(uint8 mask); // set interrupt mask
295 void setSn_MSS(uint8 s, uint16 Sn_MSSR); // set maximum segment size
296 void setSn_PROTO(uint8 s, uint8 proto); // set IP Protocol value using IP-Raw mode
297 void setSn_TTL(uint8 s, uint8 ttl);
298 uint8 getIR( void );
299 uint8 getSn_SR(uint8 s); // get socket status
300 uint8 getSn_IR(uint8 s); // get socket interrupt status
301 uint8 getSn_TSR(uint8 s);
302 uint16 getSn_TX_FSR(uint8 s); // get socket TX free buf size
303 uint16 getSn_RX_RSR(uint8 s); // get socket RX recv buf size
304 
305 void setSHAR(uint8 * addr); // set local MAC address
306 void setSIPR(uint8 * addr); // set local IP address
307 void setGAR(uint8 * addr); // set gateway address
308 void setSUBR(uint8 * addr); // set subnet mask address
309 void getSHAR(uint8 * addr); // get local MAC address
310 void getSIPR(uint8 * addr); // get local IP address
311 void getGAR(uint8 * addr); // get gateway address
312 void getSUBR(uint8 * addr); // get subnet mask address
313 
314 void getDIPR(uint8 s, uint8 *addr); // get destination IP address
315 void getDPORT(uint8 s, uint16 *port); // get destination Port number
316 
317 void clearIR(uint8 mask); // clear interrupt
318 
319 void send_data_processing(uint8 s, uint8 *wizdata, uint16 len);
320 void recv_data_processing(uint8 s, uint8 *wizdata, uint16 len);
321 void recv_data_ignore(uint8 s, uint16 len);
322 
323 uint8 incr_windowfull_retry_cnt(uint8 s);
324 void init_windowfull_retry_cnt(uint8 s);
325 
326 #endif