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w5500.c
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1 
13  //#define FILE_LOG_SILENCE
14 #include "common/common.h"
15 
16 /*
17 #include <stdio.h>
18 #include <string.h>
19 #include "config.h"
20 #include "W5500\spi2.h"
21 #include "W5500\w5500.h"
22 #include "W5500\socket.h"
23 
24 #ifdef __DEF_IINCHIP_PPP__
25  #include "md5.h"
26 #endif
27 
28 //#define CHIP_DEBUG
29 */
30 
31 //static uint8 I_STATUS[TOTAL_SOCK_NUM];
32 //static uint16 RMASK[MAX_SOCK_NUM]; //< Variable for Rx buffer MASK in each channel */
33 //static uint16 SSIZE[TOTAL_SOCK_NUM]; //< Max Tx buffer size by each channel */
34 //static uint16 RSIZE[TOTAL_SOCK_NUM]; //< Max Rx buffer size by each channel */
35 //static uint16 SBUFBASEADDRESS[MAX_SOCK_NUM]; //< Tx buffer base address by each channel */
36 //static uint16 RBUFBASEADDRESS[MAX_SOCK_NUM]; //< Rx buffer base address by each channel */
37 
38 
39 uint8 I_STATUS[TOTAL_SOCK_NUM];
40 //static uint16 RMASK[MAX_SOCK_NUM]; //< Variable for Rx buffer MASK in each channel */
41 uint16 SSIZE[TOTAL_SOCK_NUM]; //< Max Tx buffer size by each channel */
42 uint16 RSIZE[TOTAL_SOCK_NUM]; //< Max Rx buffer size by each channel */
43 //static uint16 SBUFBASEADDRESS[MAX_SOCK_NUM]; //< Tx buffer base address by each channel */
44 //static uint16 RBUFBASEADDRESS[MAX_SOCK_NUM]; //< Rx buffer base address by each channel */
45 
46 uint8 windowfull_retry_cnt[TOTAL_SOCK_NUM];
47 
48 uint8 incr_windowfull_retry_cnt(uint8 s)
49 {
50  return ++windowfull_retry_cnt[s];
51 }
52 
53 void init_windowfull_retry_cnt(uint8 s)
54 {
55  windowfull_retry_cnt[s] = 0;
56 }
57 
58 uint8 getSn_TSR(uint8 s)
59 {
60  return IINCHIP_READ_SOCKETREG(s, WIZS_TSR);
61 }
62 
63 uint8 getISR(uint8 s)
64 {
65  return I_STATUS[s];
66 }
67 
68 void putISR(uint8 s, uint8 val)
69 {
70  I_STATUS[s] = val;
71 }
72 
73 uint16 getIINCHIP_RxMAX(uint8 s)
74 {
75  return RSIZE[s];
76 }
77 
78 uint16 getIINCHIP_TxMAX(uint8 s)
79 {
80  return SSIZE[s];
81 }
82 //uint16 getIINCHIP_RxMASK(uint8 s)
83 //{
84 // return RMASK[s];
85 //}
86 //uint16 getIINCHIP_TxMASK(uint8 s)
87 //{
88 // return SMASK[s];
89 //}
90 //uint16 getIINCHIP_RxBASE(uint8 s)
91 //{
92 // return RBUFBASEADDRESS[s];
93 //}
94 //uint16 getIINCHIP_TxBASE(uint8 s)
95 //{
96 // return SBUFBASEADDRESS[s];
97 //}
98 void IINCHIP_CSoff(void)
99 {
100  //WIZ_CS(LOW);
101  //WIZ_CS2(LOW);
102  wizspi_cs(WIZ_SPI2, VAL_LOW);
103 }
104 void IINCHIP_CSon(void)
105 {
106  //WIZ_CS(HIGH);
107  //WIZ_CS2(HIGH);
108  wizspi_cs(WIZ_SPI2, VAL_HIGH);
109 }
110 uint8 IINCHIP_SpiSendData(uint8 dat)
111 {
112  //return(SPI1_SendByte(dat));
113  //return(SPI2_SendByte(dat));
114  return(wizspi_byte(WIZ_SPI2, dat));
115 }
116 
117 
118 uint8 g_rx_wr_cntl_bits = (uint8)((3&0x07)<<5) | CB_TAIL_RXBUF_WR;
119 uint8 g_rx_rd_cntl_bits = (uint8)((3%0x07)<<5) | CB_TAIL_RXBUF_RD;
120 
121 void IINCHIP_RXBUF_WRRD(uint16 addr, uint8 data)
122 {
123  uint8 rdata, redata;
124  IINCHIP_ISR_DISABLE(); // Interrupt Service Routine Disable
125 
126  //SPI MODE I/F
127  IINCHIP_CSoff(); // CS=0, SPI start
128  IINCHIP_SpiSendData((addr & 0xFF00) >> 8); // Address byte 1
129  IINCHIP_SpiSendData(addr & 0x00FF); // Address byte 2
130  IINCHIP_SpiSendData(g_rx_wr_cntl_bits); // Data write command and Write data length 1
131  IINCHIP_SpiSendData(data); // Data write (write 1byte data)
132  IINCHIP_CSon(); // CS=1, SPI end
133 
134  IINCHIP_CSoff(); // CS=0, SPI start
135  IINCHIP_SpiSendData((addr & 0xFF00) >> 8); // Address byte 1
136  IINCHIP_SpiSendData(addr & 0x00FF); // Address byte 2
137  IINCHIP_SpiSendData(g_rx_rd_cntl_bits); // Data read command and Read data length 1
138  rdata = IINCHIP_SpiSendData(0x00); // Data read (read 1byte data)
139  IINCHIP_CSon(); // CS=1, SPI end
140 
141  IINCHIP_ISR_ENABLE(); // Interrupt Service Routine Enable
142 
143  if( rdata != data )
144  {
145  printf("addr:%X, data:%X, rdata:%X, ", addr, data, rdata);
146  IINCHIP_ISR_DISABLE(); // Interrupt Service Routine Disable
147  IINCHIP_CSoff(); // CS=0, SPI start
148  IINCHIP_SpiSendData((addr & 0xFF00) >> 8); // Address byte 1
149  IINCHIP_SpiSendData(addr & 0x00FF); // Address byte 2
150  IINCHIP_SpiSendData(g_rx_rd_cntl_bits); // Data read command and Read data length 1
151  redata = IINCHIP_SpiSendData(0x00); // Data read (read 1byte data)
152  IINCHIP_CSon(); // CS=1, SPI end
153  IINCHIP_ISR_ENABLE(); // Interrupt Service Routine Enable
154  printf("redata:%X \r\n", redata);
155  }
156 }
157 
158  /*
159 @brief This function writes the data into W5200 registers.
160 */
161 void IINCHIP_WRITE(uint16 addr, uint8 cntl_bits, uint8 data)
162 {
163  IINCHIP_ISR_DISABLE(); // Interrupt Service Routine Disable
164  //SPI MODE I/F
165  IINCHIP_CSoff(); // CS=0, SPI start
166  IINCHIP_SpiSendData((addr & 0xFF00) >> 8); // Address byte 1
167  IINCHIP_SpiSendData(addr & 0x00FF); // Address byte 2
168  IINCHIP_SpiSendData(cntl_bits); // Data write command and Write data length 1
169  IINCHIP_SpiSendData(data); // Data write (write 1byte data)
170  IINCHIP_CSon(); // CS=1, SPI end
171  IINCHIP_ISR_ENABLE(); // Interrupt Service Routine Enable
172 }
173 /*
174 @brief This function reads the value from W5200 registers.
175 */
176 uint8 IINCHIP_READ(uint16 addr, uint8 cntl_bits)
177 {
178  uint8 data = 0;
179  IINCHIP_ISR_DISABLE(); // Interrupt Service Routine Disable
180  IINCHIP_CSoff(); // CS=0, SPI start
181  IINCHIP_SpiSendData((addr & 0xFF00) >> 8); // Address byte 1
182  IINCHIP_SpiSendData(addr & 0x00FF); // Address byte 2
183  IINCHIP_SpiSendData(cntl_bits); // Data read command and Read data length 1
184  data = IINCHIP_SpiSendData(0x00); // Data read (read 1byte data)
185  IINCHIP_CSon(); // CS=1, SPI end
186  IINCHIP_ISR_ENABLE(); // Interrupt Service Routine Enable
187  return data;
188 }
189 
190 void IINCHIP_WRITE_SEQ(uint16 addr, uint8 cntl_bits, uint16 len, uint8 * data)
191 {
192  uint16 idx = 0;
193 #ifdef CHIP_DEBUG
194  uint16 count = 0;
195 #endif
196 
197 #if 0
198  if(len == 0)
199  {
200  printf("Unexpected1 length 0\r\n");
201  }
202 #endif
203 
204  IINCHIP_ISR_DISABLE();
205  //SPI MODE I/F
206  IINCHIP_CSoff(); // CS=0, SPI start
207  IINCHIP_SpiSendData((addr & 0xFF00) >> 8); // Address byte 1
208  IINCHIP_SpiSendData(addr & 0x00FF); // Address byte 2
209  IINCHIP_SpiSendData(cntl_bits); // Control bit
210  for(idx = 0; idx < len; idx++) // Write data in loop
211  {
212  IINCHIP_SpiSendData(data[idx]);
213  }
214  IINCHIP_CSon(); // CS=1, SPI end
215  IINCHIP_ISR_ENABLE(); // Interrupt Service Routine Enable
216 
217 #ifdef CHIP_DEBUG
218  for(idx=0; idx< len; idx++)
219  {
220  if(data[idx] == 0)
221  count++;
222  if(count > 3)
223  {
224  printf("SEQ read pattern Error");
225  while(1);
226  }
227  }
228 #endif
229 
230 }
231 
232 void IINCHIP_READ_SEQ(uint16 addr, uint8 cntl_bits, uint16 len, uint8 * data)
233 {
234  uint16 idx = 0;
235 
236 #ifdef CHIP_DEBUG
237  uint16 count = 0;
238 #endif
239 
240  if(len == 0)
241  {
242  printf("Unexpected2 length 0\r\n");
243  }
244 
245  //printf("IINCHIP_READ_SEQ->addr: %X, len : %d \r\n", addr, len);
246  IINCHIP_ISR_DISABLE();
247  //SPI MODE I/F
248  IINCHIP_CSoff(); // CS=0, SPI start
249  IINCHIP_SpiSendData((addr & 0xFF00) >> 8); // Address byte 1
250  IINCHIP_SpiSendData(addr & 0x00FF); // Address byte 2
251  IINCHIP_SpiSendData(cntl_bits); // Control bit
252  for(idx = 0; idx < len; idx++) // Write data in loop
253  {
254  data[idx] = IINCHIP_SpiSendData(0x00);
255  }
256  IINCHIP_CSon(); // CS=1, SPI end
257  IINCHIP_ISR_ENABLE(); // Interrupt Service Routine Enable
258 }
259 
260 
261 void IINCHIP_WRITE_COMMON( uint16 addr, uint8 data)
262 {
263  uint8 cntl_bits = 0;
264  cntl_bits = CB_TAIL_COMREG_WR;
265  IINCHIP_WRITE(addr, cntl_bits, data);
266 }
267 
268 uint8 IINCHIP_READ_COMMON(uint16 addr)
269 {
270  uint8 data = 0;
271  uint8 cntl_bits = 0;
272  cntl_bits = CB_TAIL_COMREG_RD;
273  data = IINCHIP_READ(addr, cntl_bits);
274  return data;
275 }
276 
277 
278 void IINCHIP_WRITE_DM( uint16 addr, uint8 data)
279 {
280  uint8 cntl_bits = 0;
281  cntl_bits = CM_MEM_DM;
282  IINCHIP_WRITE(addr, cntl_bits, data);
283 }
284 
285 uint8 IINCHIP_READ_DM(uint16 addr)
286 {
287  uint8 data = 0;
288  uint8 cntl_bits = 0;
289  cntl_bits = CM_MEM_DM;
290  data = IINCHIP_READ(addr, cntl_bits);
291  return data;
292 }
293 
294 void IINCHIP_READ_COMMON_SEQ(uint16 addr, uint8 len, uint8 * data)
295 {
296  uint8 cntl_bits = 0;
297  cntl_bits = (uint8)CB_TAIL_COMMONREG_RD_SEQ;
298  IINCHIP_READ_SEQ(addr, cntl_bits, len, (uint8 *)data);
299 }
300 
301 void IINCHIP_WRITE_COMMON_SEQ(uint16 addr, uint8 len, uint8 * data)
302 {
303  uint8 cntl_bits = 0;
304  cntl_bits = (uint8)CB_TAIL_COMMONREG_WR_SEQ;
305  IINCHIP_WRITE_SEQ(addr, cntl_bits, len, (uint8 *)data);
306 }
307 
308 void IINCHIP_WRITE_SOCKETREG(uint8 sock_num, uint16 addr, uint8 data)
309 {
310  uint8 cntl_bits = 0;
311  cntl_bits = (uint8)((sock_num&0x07)<<5) | CB_TAIL_SOCKETREG_WR;
312  //printf("cntl_bits %X \r\n", cntl_bits);
313  IINCHIP_WRITE(addr, cntl_bits, data);
314 }
315 
316 uint8 IINCHIP_READ_SOCKETREG(uint8 sock_num, uint16 addr)
317 {
318  uint8 data = 0;
319  uint8 cntl_bits = 0;
320  cntl_bits = (uint8)((sock_num&0x07)<<5) | CB_TAIL_SOCKETREG_RD;
321  //printf("cntl_bits %X \r\n", cntl_bits);
322  data = IINCHIP_READ(addr, cntl_bits);
323  return data;
324 }
325 
326 
327 void IINCHIP_READ_SOCKETREG_SEQ(uint8 sock_num, uint16 addr, uint8 len, uint8 * data)
328 {
329  uint8 cntl_bits = 0;
330  cntl_bits = (uint8)((sock_num&0x07)<<5) | CB_TAIL_SOCKETREG_RD_SEQ;
331  IINCHIP_READ_SEQ(addr, cntl_bits, len, (uint8 *)data);
332 }
333 
334 void IINCHIP_WRITE_SOCKETREG_SEQ(uint8 sock_num, uint16 addr, uint8 len, uint8 * data)
335 {
336  uint8 cntl_bits = 0;
337  cntl_bits = (uint8)((sock_num&0x07)<<5) | CB_TAIL_SOCKETREG_WR_SEQ;
338 
339  IINCHIP_WRITE_SEQ(addr, cntl_bits, len, (uint8 *)data);
340 }
341 
342 void IINCHIP_WRITE_TXBUF(uint8 sock_num, uint16 addr, uint8 data)
343 {
344  uint8 cntl_bits = 0;
345  cntl_bits = (uint8)((sock_num&0x07)<<5) | CB_TAIL_TXBUF_WR;
346  IINCHIP_WRITE(addr, cntl_bits, data);
347 }
348 
349 uint8 IINCHIP_READ_TXBUF(uint8 sock_num, uint16 addr)
350 {
351  uint8 cntl_bits = 0;
352  uint8 data = 0;
353  cntl_bits = (uint8)((sock_num&0x07)<<5) | CB_TAIL_TXBUF_RD;
354  data = IINCHIP_READ(addr, cntl_bits);
355  return data;
356 }
357 
358 void IINCHIP_WRITE_RXBUF(uint8 sock_num, uint16 addr, uint8 data)
359 {
360  uint8 cntl_bits = 0;
361  cntl_bits = (uint8)((sock_num&0x07)<<5) | CB_TAIL_RXBUF_WR;
362  IINCHIP_WRITE(addr, cntl_bits, data);
363 }
364 
365 uint8 IINCHIP_READ_RXBUF(uint8 sock_num, uint16 addr)
366 {
367  uint8 cntl_bits = 0;
368  uint8 data = 0;
369  cntl_bits = (uint8)((sock_num&0x07)<<5) | CB_TAIL_RXBUF_RD;
370  data = IINCHIP_READ(addr, cntl_bits);
371  return data;
372 }
373 
374 void IINCHIP_WRITE_TXBUF_SEQ(uint8 sock_num, uint16 addr, uint16 len, uint8 * data)
375 {
376  uint8 cntl_bits = 0;
377  cntl_bits = (uint8)((sock_num&0x07)<<5) | CB_TAIL_TXBUF_WR_SEQ;
378  IINCHIP_WRITE_SEQ(addr, cntl_bits, len, (uint8 *)data);
379 }
380 
381 void IINCHIP_READ_TXBUF_SEQ(uint8 sock_num, uint16 addr, uint16 len, uint8 * data)
382 {
383  uint8 cntl_bits = 0;
384  cntl_bits = (uint8)((sock_num&0x07)<<5) | CB_TAIL_TXBUF_RD_SEQ;
385  IINCHIP_READ_SEQ(addr, cntl_bits, len, data);
386 }
387 
388 void IINCHIP_WRITE_RXBUF_SEQ(uint8 sock_num, uint16 addr, uint16 len, uint8 * data)
389 {
390  uint8 cntl_bits = 0;
391  cntl_bits = (uint8)((sock_num&0x07)<<5) | CB_TAIL_RXBUF_WR_SEQ;
392  IINCHIP_WRITE_SEQ(addr, cntl_bits, len, data);
393 }
394 
395 void IINCHIP_READ_RXBUF_SEQ(uint8 sock_num, uint16 addr, uint16 len, uint8 * data)
396 {
397  uint8 cntl_bits = 0;
398  cntl_bits = (uint8)((sock_num&0x07)<<5) | CB_TAIL_RXBUF_RD_SEQ;
399  IINCHIP_READ_SEQ(addr, cntl_bits, len, data);
400 }
401 
402 
403 
404 // added
405 
406 /*
407 @brief This function sets up gateway IP address.
408 */
409 void setGAR(
410  uint8 * addr //< a pointer to a 4 -byte array responsible to set the Gateway IP address. */
411  )
412 {
413  IINCHIP_WRITE_COMMON( (WIZC_GAR0 + 0), addr[0]);
414  //printf("%d -- rd: %X \r\n", 0, IINCHIP_READ_COMMON( (WIZC_GAR0 + 0) ) );
415  //IINCHIP_WRITE_COMMON( (WIZC_GAR0 + 0), 0x01);
416  IINCHIP_WRITE_COMMON( (WIZC_GAR0 + 1), addr[1]);
417  //printf("%d -- rd: %X \r\n", 1, IINCHIP_READ_COMMON( (WIZC_GAR0 + 1) ));
418  //IINCHIP_WRITE_COMMON( (WIZC_GAR0 + 1), 0x02);
419  IINCHIP_WRITE_COMMON( (WIZC_GAR0 + 2), addr[2]);
420  //printf("%d -- rd: %X \r\n", 2, IINCHIP_READ_COMMON( (WIZC_GAR0 + 2) ));
421  //IINCHIP_WRITE_COMMON( (WIZC_GAR0 + 2), 0x03);
422  IINCHIP_WRITE_COMMON( (WIZC_GAR0 + 3), addr[3]);
423  //printf("%d -- rd: %X \r\n", 3, IINCHIP_READ_COMMON( (WIZC_GAR0 + 3) ));
424  //IINCHIP_WRITE_COMMON( (WIZC_GAR0 + 3), 0x04);
425 
426 #if 0
427  uint16 j =0;
428  printf("COMMON REG\r\n");
429  for(j=1; j<7; j++)
430  {
431  printf("%d -- rd: %X ", j, IINCHIP_READ_COMMON( j ) );
432  IINCHIP_WRITE_COMMON( j, 0x00+j);
433  printf("wr:%X, rd:%X \r\n", j, IINCHIP_READ_COMMON( j ) );
434  }
435 #endif
436 }
437 
438 /*
439 void getGWIP(uint8 * addr)
440 {
441  addr[0] = IINCHIP_READ_COMMON( (WIZC_GAR0 + 0));
442  addr[1] = IINCHIP_READ_COMMON( (WIZC_GAR0 + 1));
443  addr[2] = IINCHIP_READ_COMMON( (WIZC_GAR0 + 2));
444  addr[3] = IINCHIP_READ_COMMON( (WIZC_GAR0 + 3));
445 }
446 */
447 
448 /*
449 @brief It sets up SubnetMask address
450 */
451 void setSUBR(uint8 * addr)
452 {
453  IINCHIP_WRITE_COMMON( (WIZC_SUBR0 + 0), addr[0]);
454  IINCHIP_WRITE_COMMON( (WIZC_SUBR0 + 1), addr[1]);
455  IINCHIP_WRITE_COMMON( (WIZC_SUBR0 + 2), addr[2]);
456  IINCHIP_WRITE_COMMON( (WIZC_SUBR0 + 3), addr[3]);
457 }
458 
459 /*
460 @brief This function sets up MAC address.
461 */
462 void setSHAR(
463  uint8 * addr //< a pointer to a 6 -byte array responsible to set the MAC address. */
464  )
465 {
466  IINCHIP_WRITE_COMMON((WIZC_SHAR0 + 0),addr[0]);
467  IINCHIP_WRITE_COMMON((WIZC_SHAR0 + 1),addr[1]);
468  IINCHIP_WRITE_COMMON((WIZC_SHAR0 + 2),addr[2]);
469  IINCHIP_WRITE_COMMON((WIZC_SHAR0 + 3),addr[3]);
470  IINCHIP_WRITE_COMMON((WIZC_SHAR0 + 4),addr[4]);
471  IINCHIP_WRITE_COMMON((WIZC_SHAR0 + 5),addr[5]);
472 }
473 
474 /*
475 @brief This function sets up Source IP address.
476 */
477 void setSIPR(
478  uint8 * addr //< a pointer to a 4 -byte array responsible to set the Source IP address. */
479  )
480 {
481  IINCHIP_WRITE_COMMON((WIZC_SIPR0 + 0),addr[0]);
482  IINCHIP_WRITE_COMMON((WIZC_SIPR0 + 1),addr[1]);
483  IINCHIP_WRITE_COMMON((WIZC_SIPR0 + 2),addr[2]);
484  IINCHIP_WRITE_COMMON((WIZC_SIPR0 + 3),addr[3]);
485 }
486 
487 /*
488 @brief This function sets up Source IP address.
489 */
490 void getGAR(uint8 * addr)
491 {
492  addr[0] = IINCHIP_READ_COMMON(WIZC_GAR0);
493  addr[1] = IINCHIP_READ_COMMON(WIZC_GAR0+1);
494  addr[2] = IINCHIP_READ_COMMON(WIZC_GAR0+2);
495  addr[3] = IINCHIP_READ_COMMON(WIZC_GAR0+3);
496 }
497 void getSUBR(uint8 * addr)
498 {
499  addr[0] = IINCHIP_READ_COMMON(WIZC_SUBR0);
500  addr[1] = IINCHIP_READ_COMMON(WIZC_SUBR0+1);
501  addr[2] = IINCHIP_READ_COMMON(WIZC_SUBR0+2);
502  addr[3] = IINCHIP_READ_COMMON(WIZC_SUBR0+3);
503 }
504 void getSHAR(uint8 * addr)
505 {
506  addr[0] = IINCHIP_READ_COMMON(WIZC_SHAR0);
507  addr[1] = IINCHIP_READ_COMMON(WIZC_SHAR0+1);
508  addr[2] = IINCHIP_READ_COMMON(WIZC_SHAR0+2);
509  addr[3] = IINCHIP_READ_COMMON(WIZC_SHAR0+3);
510  addr[4] = IINCHIP_READ_COMMON(WIZC_SHAR0+4);
511  addr[5] = IINCHIP_READ_COMMON(WIZC_SHAR0+5);
512 }
513 void getSIPR(uint8 * addr)
514 {
515  addr[0] = IINCHIP_READ_COMMON(WIZC_SIPR0);
516  addr[1] = IINCHIP_READ_COMMON(WIZC_SIPR0+1);
517  addr[2] = IINCHIP_READ_COMMON(WIZC_SIPR0+2);
518  addr[3] = IINCHIP_READ_COMMON(WIZC_SIPR0+3);
519 }
520 
521 void getDIPR(uint8 s, uint8 *addr)
522 {
523  addr[0] = IINCHIP_READ_SOCKETREG(s, WIZS_DIPR0 + 0);
524  addr[1] = IINCHIP_READ_SOCKETREG(s, WIZS_DIPR0 + 1);
525  addr[2] = IINCHIP_READ_SOCKETREG(s, WIZS_DIPR0 + 2);
526  addr[3] = IINCHIP_READ_SOCKETREG(s, WIZS_DIPR0 + 3);
527  //addr[0] = IINCHIP_READ(WIZ_SOCK_REG(s, WIZS_DIPR0));
528  //addr[1] = IINCHIP_READ(WIZ_SOCK_REG(s, WIZS_DIPR1));
529  //addr[2] = IINCHIP_READ(WIZ_SOCK_REG(s, WIZS_DIPR2));
530  //addr[3] = IINCHIP_READ(WIZ_SOCK_REG(s, WIZS_DIPR3));
531 }
532 
533 void getDPORT(uint8 s, uint16 *port)
534 {
535  *port = IINCHIP_READ_SOCKETREG(s, WIZS_DPORT0 + 0) << 8;
536  *port += IINCHIP_READ_SOCKETREG(s, WIZS_DPORT0 + 1);
537  //*port = IINCHIP_READ(WIZ_SOCK_REG(s, WIZS_DPORT0)) << 8;
538  //*port += IINCHIP_READ(WIZ_SOCK_REG(s, WIZS_DPORT1));
539 }
540 
541 void setMR(uint8 val)
542 {
543  IINCHIP_WRITE_COMMON(WIZC_MR, val);
544 }
545 
546 /*
547 @brief This function gets Interrupt register in common register.
548  */
549 uint8 getIR( void )
550 {
551  return IINCHIP_READ_COMMON(WIZC_IR);
552 }
553 
554 
555 /*
556  Retransmittion
557  */
558 
559 /*
560 @brief This function sets up Retransmission time.
561 
562 If there is no response from the peer or delay in response then retransmission
563 will be there as per RTR (Retry Time-value Register)setting
564 */
565 void setRTR(uint16 timeout)
566 {
567  IINCHIP_WRITE_COMMON(WIZC_RTR0,(uint8)((timeout & 0xff00) >> 8));
568  IINCHIP_WRITE_COMMON((WIZC_RTR0 + 1),(uint8)(timeout & 0x00ff));
569 }
570 
571 /*
572 @brief This function set the number of Retransmission.
573 
574 If there is no response from the peer or delay in response then recorded time
575 as per RTR & RCR register seeting then time out will occur.
576 */
577 void setRCR(uint8 retry)
578 {
579  IINCHIP_WRITE_COMMON(WIZC_RCR,retry);
580 }
581 
582 /*
583 @brief This function set the interrupt mask Enable/Disable appropriate Interrupt. ('1' : interrupt enable)
584 
585 If any bit in IMR is set as '0' then there is not interrupt signal though the bit is
586 set in IR register.
587 */
588 void setIMR(uint8 mask)
589 {
590  IINCHIP_WRITE_COMMON(WIZC_IMR, mask); // must be setted 0x10.
591 }
592 
593 /*
594 @brief This function set the interrupt mask Enable/Disable appropriate Interrupt. ('1' : interrupt enable)
595 
596 If any bit in IMR is set as '0' then there is not interrupt signal though the bit is
597 set in IR register.
598 */
599 void clearIR(uint8 mask)
600 {
601  IINCHIP_WRITE_COMMON(WIZC_IR, ~mask | getIR() ); // must be setted 0x10.
602 }
603 
604 /*
605 @brief This sets the maximum segment size of TCP in Active Mode), while in Passive Mode this is set by peer
606 */
607 void setSn_MSS(uint8 s, uint16 Sn_MSSR)
608 {
609  IINCHIP_WRITE_SOCKETREG( s, WIZS_MSSR0 ,(uint8)((Sn_MSSR & 0xff00) >> 8));
610  IINCHIP_WRITE_SOCKETREG( s,(WIZS_MSSR0 + 1),(uint8)(Sn_MSSR & 0x00ff));
611 }
612 
613 void setSn_TTL(uint8 s, uint8 ttl)
614 {
615  IINCHIP_WRITE_SOCKETREG( s, WIZS_TTL , ttl);
616 }
617 
618 /*
619 @brief get socket interrupt status
620 
621 These below functions are used to read the Interrupt & Soket Status register
622 */
623 uint8 getSn_IR(uint8 s)
624 {
625  return IINCHIP_READ_SOCKETREG(s, WIZS_IR );
626 }
627 
628 
629 /*
630 @brief get socket status
631 */
632 uint8 getSn_SR(uint8 s)
633 {
634  return IINCHIP_READ_SOCKETREG(s, WIZS_SR );
635 }
636 
637 
638 /*
639 @brief get socket TX free buf size
640 
641 This gives free buffer size of transmit buffer. This is the data size that user can transmit.
642 User shuold check this value first and control the size of transmitting data
643 */
644 uint16 getSn_TX_FSR(uint8 s)
645 {
646  uint16 val=0,val1=0;
647  do
648  {
649  val1 = IINCHIP_READ_SOCKETREG(s, WIZS_TX_FSR0 );
650  val1 = (val1 << 8) + IINCHIP_READ_SOCKETREG(s, WIZS_TX_FSR0 + 1);
651  if (val1 != 0)
652  {
653  val = IINCHIP_READ_SOCKETREG(s, WIZS_TX_FSR0 );
654  val = (val << 8) + IINCHIP_READ_SOCKETREG(s, WIZS_TX_FSR0 + 1);
655  }
656  } while (val != val1);
657  return val;
658 }
659 
660 
661 /*
662 @brief get socket RX recv buf size
663 
664 This gives size of received data in receive buffer.
665 */
666 uint16 getSn_RX_RSR(uint8 s)
667 {
668  uint16 val=0,val1=0;
669  do
670  {
671  val1 = IINCHIP_READ_SOCKETREG( s, WIZS_RX_RSR0 );
672  val1 = (val1 << 8) + IINCHIP_READ_SOCKETREG( s, WIZS_RX_RSR0 + 1);
673  if(val1 != 0)
674  {
675  val = IINCHIP_READ_SOCKETREG(s, WIZS_RX_RSR0 );
676  val = (val << 8) + IINCHIP_READ_SOCKETREG(s, WIZS_RX_RSR0 + 1);
677  }
678  } while (val != val1);
679  return val;
680 }
681 
682 
683 /*
684 @brief This function is being called by send() and sendto() function also.
685 
686 This function read the Tx write pointer register and after copy the data in buffer update the Tx write pointer
687 register. User should read upper byte first and lower byte later to get proper value.
688 */
689 void send_data_processing(uint8 s, uint8 *data, uint16 len)
690 {
691  if(len == 0)
692  {
693  printf("CH: %d Unexpected1 length 0\r\n", s);
694  return;
695  }
696 
697  uint16 ptr = 0;
698  ptr = IINCHIP_READ_SOCKETREG( s, WIZS_TX_WR0 );
699  ptr = ((ptr & 0x00ff) << 8) + IINCHIP_READ_SOCKETREG( s, WIZS_TX_WR0 + 1);
700  //printf("TX ptr : %X ", ptr);
701  IINCHIP_WRITE_TXBUF_SEQ(s, ptr, len, data);
702  ptr += len;
703  IINCHIP_WRITE_SOCKETREG( s,WIZS_TX_WR0 ,(uint8)((ptr & 0xff00) >> 8));
704  IINCHIP_WRITE_SOCKETREG( s,(WIZS_TX_WR0 + 1),(uint8)(ptr & 0x00ff));
705 }
706 
707 
708 /*
709 @brief This function is being called by recv() also.
710 
711 This function read the Rx read pointer register
712 and after copy the data from receive buffer update the Rx write pointer register.
713 User should read upper byte first and lower byte later to get proper value.
714 */
715 void recv_data_processing(uint8 s, uint8 *data, uint16 len)
716 {
717  uint16 ptr = 0;
718 
719  if(len == 0)
720  {
721  printf("CH: %d Unexpected2 length 0\r\n", s);
722  return;
723  }
724 
725  ptr = IINCHIP_READ_SOCKETREG( s, WIZS_RX_RD0 );
726  ptr = ((ptr & 0x00ff) << 8) + IINCHIP_READ_SOCKETREG( s, WIZS_RX_RD0 + 1);
727 
728  //printf("RX ptr : %X ", ptr);
729  IINCHIP_READ_RXBUF_SEQ(s, ptr, len, data);
730  ptr += len;
731  //printf("RX ptr : %X \r\n", ptr);
732 
733  IINCHIP_WRITE_SOCKETREG( s, WIZS_RX_RD0 ,(uint8)((ptr & 0xff00) >> 8));
734  IINCHIP_WRITE_SOCKETREG( s, WIZS_RX_RD0 + 1,(uint8)(ptr & 0x00ff));
735 }
736 
737 
738 void recv_data_ignore(uint8 s, uint16 len)
739 {
740  uint16 ptr;
741 
742  ptr = IINCHIP_READ_SOCKETREG(s, WIZS_RX_RD0 + 0);
743  ptr = ((ptr & 0x00ff) << 8) + IINCHIP_READ_SOCKETREG(s, WIZS_RX_RD0 + 1);
744  ptr += len;
745  IINCHIP_WRITE_SOCKETREG(s, WIZS_RX_RD0 + 0, (uint8)((ptr & 0xff00) >> 8));
746  IINCHIP_WRITE_SOCKETREG(s, WIZS_RX_RD0 + 1, (uint8)(ptr & 0x00ff));
747 }
748 
749 
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